1. Field of the Invention
The present invention relates to technology for non-volatile memory.
2. Description of the Related Art
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. Pat. No. 6,859,397, titled “Source Side Self-Boosting Technique For Non-Volatile Memory,” and U.S. Pat. No. 6,917,545, titled “Detecting Over Programmed Memory,” both of which are incorporated herein by reference in their entirety.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (an erased state and a programmed state). Such a flash memory device is sometimes referred to as a binary flash memory device.
A multi-state flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges separated by forbidden ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device.
Shifts in the apparent charge stored on a floating gate can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates. This floating gate to floating gate coupling phenomena is described in U.S. Pat. No. 5,867,429, which is incorporated herein by reference in its entirety. One example of an adjacent floating gate to a target floating gate includes a floating gate that is connected to the same word line and connected to an adjacent bit line.
The effect of the floating gate to floating gate coupling is of greater concern for multi-state devices because in multi-state devices the allowed threshold voltage ranges and the forbidden ranges are narrower than in binary devices. Therefore, the floating gate to floating gate coupling can result in memory cells being shifted from an allowed threshold voltage range to a forbidden range.
The floating gate to floating gate coupling can occur between sets of adjacent memory cells that have been programmed at different times. For example, a first memory cell is programmed to add a level of charge to its floating gate that corresponds to one set of data. Subsequently, one or more adjacent memory cells are programmed to add a level of charge to their floating gates that correspond to a second set of data. After the one or more of the adjacent memory cells are programmed, the charge level read from the first memory cell appears to be different than programmed because of the effect of the charge on the adjacent memory cells being coupled to the first memory cell. The coupling from adjacent memory cells can shift the apparent charge level being read a sufficient amount to lead to an erroneous reading of the data stored.
The floating gate to floating gate coupling can also occur between sets of adjacent memory cells that have been programmed concurrently. For example, two adjacent multi-state memory cells may be programmed to different target levels such that a first memory cell is programmed to a state corresponding to a lower threshold voltage and a second memory cell is programmed to a state corresponding to a higher threshold voltage. The memory cell being programmed to the state corresponding to the lower threshold voltage is likely to reach that state and be locked out from further programming before the second memory cell reaches the state corresponding to the higher threshold voltage. After the second memory cell reaches the state corresponding to the higher threshold voltage, it will couple to the first memory cell and cause the first memory cell to have a higher apparent threshold voltage than programmed.
As memory cells continue to shrink in size, the natural programming and erase distributions of threshold voltages are expected to increase due to short channel effects, greater oxide thickness/coupling ratio variations and more channel dopant fluctuations, thereby reducing the available separation between adjacent states. This effect is much more significant for multi-state memories than memories using only two states (binary memories). Furthermore, the reduction of the space between word lines and of the space between bit lines will also increase the coupling between adjacent floating gates.
Thus, there is a need to reduce the effects of coupling between adjacent floating gates.